July 8, 2013, IMEC Technology Forum, San Francisco—Kurt Ronse from Imec talked about mastering patterning costs for future technology nodes. The biggest problems are that the technical requirements do not map well into any available technologies.
Currently, 193 nm immersion lithography with multiple patterning is the workhorse technology. EUV is not ready for production, and there are no viable alternatives within the working time horizon that can take over from 193nm. The roadmap to 10nm focuses on the middle and via layers where cost dominates. These layers are the first candidates for EUV.
Today, the 20nm node requires double patterning with a lithography-etch-lithography -etch (LELE) flow. At 10nm, this becomes a LELELE with a self-aligned structures, or a single exposure with EUV. The immersion processes require more steps and more layers with greatly increased complexity and costs. Additional costs include the number of masks, the specifications for those masks, and the requirements for higher scanner performance.
The pattern stack requires two patterns plus a trim step plus a sacrificial fill for all of the multiple patterning layers. For triple patterning, these lithography steps must be repeated three times plus 2 trim steps between patterning steps. The layout for these layers must be constructivists these three separate portions, all pattern aware, per layer of metal and via.
As a result, moving to a 10nm process with triple patterning will cost 180 percent of the processing for a 28nm process. By switching to EUV, the penalty is only 120 percent. These penalties do not take into account the increasing number of masks for any particular process. A 28nm device requires 10 masks, a 20nm device takes 12, while a 10nm device with 193nm immersion will require at least 22 masks. Changing to EUV brings the masks back to 10, but and EUV mask will cost 1.75 times a 20 nanometer mask.
With the increased processing, at 10nm, EUV throughput is equal to 193nm immersion at about 50 wafers per hour. The cost for the improve scanners unmasks may also be equivalent. The challenges for overlay and focus control for the immersion technologies will be daunting, and the costs of this equipment will reflect these difficulties. Therefore, we need to change to EUV at 10nm to reduce scanner costs, number of masks, and create simpler patterns that do not need to be multi-pattern aware.
The big question is, will EUV be ready? The current resists are capable of resolving lines well below 10nm. Pattern collapses a major resolution limiting factor for single patterning, while local critical dimension uniformity is now below 2nm. One solution to both of these issues is to increase exposure times, while an alternative is to find new resists and improve image contrast. Improvements are possible through etch resist defectivity reduction as well as improvements in the masks themselves. Changes in process flow can improve local critical dimension uniformity by post processing.
Machine to machine overlay alignment in both EUV and immersion have to get below 6 nm. This requirement is based on the assumption that not all lithography steps will be carried out on the same machine. In fact, it is likely that some steps will still be done in 193nm immersion while others were being EUV. EUV power is expected to reach 80 W by the end of this year. Some machines have achieved 50W for up to one hour, but for full production, EUV must be at least 250W.
An alternative to any of these problematic lithography challenges is to consider directed self-assembly (DSA). They are making significant progress in these techniques, and the technology shows great promise within the 10 nm process timeline. The big problem is that EUV may still be required for patterning. A lot of issues including overlay accuracy, opening process windows, and defectivity still need a lot of time and development. DSA could still work on 7nm FINFETs. Current projects are getting 2.6nm line width roughness.
