July, 7, 2014, IMEC Technology Forum, San Francisco—Bobby Bell from KLA-Tencor talked about the exponentially changing technologies underlying the next generations of semiconductor manufacturing. The economics of the industry are presenting rapidly rising costs and are driving further industry consolidation.
The trend of lower costs per gate is no longer valid as the process technologies move below 20nm. one major factor is the wafer yield is dropping faster than the increased in die count, .leading to increased die costs. The yield is a function of the confluence of the following factors: 3-D devices, multiple patterning steps per layer, scaling challenges, new materials, a lack of EUV production equipment, variability, and metrology.
To make the situation worse, all of the costs for equipment and materials are increasing as the needs for higher purity materials and higher precision equipment take over the cost structures. The number of manufacturers who will be moving to the next generation of equipment and processes will be smaller than any previous generation, possibly less than 10 companies.
As a result, the industry must increase collaboration to reduce friction and risk for the next generation processes. The pre-competitive collaboration must address the growing process complexity of each module and layer, to permit the development of high-commonality processing equipment. The designs will have to become more robust through realistic design rules and methodologies, to include qualified component libraries. The leaf cells have to be evaluated for weak points like variability, critical areas, edge variability, and pattern control. Only with all of these factors in place can the potential for successful first silicon be realized.
The qualifications of the components and features now have to take into account the entire stack and not just the layer. Process variability will affect other layers and non-planarity and nano-topologies will only add to the challenges. The 1x nm processes, going down to 7 and 5nm, will have to consider the atomic nature of the materials and devices. The increasing number of process steps will asymptotically drive the process windows to zero without significant pattern integration processing.
For example, the critical dimension (CD) and overlay budgets shown in the table lead to the conclusion that over half of the budgets are due to non-lithographic issues.
| Process | 28nm | 20nm | 14nm | 10nm |
| Overlay | 9 nm | 6 nm | 4.5nm | 3.1nm |
| CD | 4.5nm | 3 nm | 2 nm | 1.3nm |
One possible solution is to use analytics and a closed –loop evaluation process to qualify designs and design elements. Such factors as wafer shape and flatness come into play at these dimensions and have a big impact on overlay registration.
Also, the design needs to be checked for more than just functionality. The entirety of a typical design and its elements represent 30-300M weak points. Defect size is approaching the lower limit of design rules, and there are more defect types in the latest flows. Full wafer defect coverage needs to get beyond 1 wafer per hour at an affordable cost.
The use of e-beam technologies for inspection is marginally viable. Inspecting a wafer reticule can take over 7 days with e-beam. Alternative technologies for inspection are moving to optical techniques. The newest tools use high-power industrial lasers as triggers for plasma sources and change to dark-field views and variable, pixilated apertures to generate images for high-resolution optics and high-speed image processing. The algorithms need to consider the design to identify critical areas for detailed inspection.
This design-based inspection is necessary because the design provides the context for the inspection. The high-resolution is only at those critical areas to allow high resolution inspection and detection in small areas to speed up the inspections. The concept of cross-process modules allows design correlation with wafer inspection. The partnership with IMEC includes work on wafer geometry control, integrated CD and overlay efforts, new material defects, and improved algorithms for integrated process and inspection flows.