December 16, 2014, IEDM, Sn Francisco—Chih-Ming Hung from MediaTek talked about the changes in architectures to implement RF transceivers to minimize the effects of device variability and process variations. The added intelligence is still constrained by the need for some device matching and device level enhancements.
The strong demand for high performance affordable handsets has spurred the requirement of using plain vanilla CMOS for RF.A block diagram of a fully-integrated SoC consists of multiple radios, processor units, power management units, and a variety of peripherals. Since logic gates occupy most of the area, Moore’s Law ripples through to analog circuits on the same die and any process mask adder only for RF is prohibited. However, there are growing analog impairments in advanced nodes greatly impacting circuit performance and cost due to worse device matching and tighter design rules on maximum poly density, minimum dummy fills, etc.
Digital techniques have to be exploited to stay with or better than Moore’s Law. Furthermore, along process technology scaling, the increase of ft, the decrease of voltage headroom, and the reduction of transistor cost call for a paradigm shift from continuous-time (CT) to discrete-time (DT) operations to take advantages of digitally-intensive architectures where mixed-signal circuits are replaced by logic gates and algorithms natural in digital CMOS.
A generic transceiver has a local oscillator (LO) to generate precise RF frequencies that are synchronized with basestations. The transmitter sends RF signals to the air, and the receiver demodulates information from the antenna. Changing from analog to a discrete-time receiver (DRX) brings the power of DSP to the RF domain and uses only device components from standard digital CMOS. The DT passive filter can easily be reconfigured with different orders and shapes, and can attain voltage gain by stacking capacitors. Because there are only switches and capacitors, tradeoffs are possible among voltage headroom, amplifier bandwidth, and linearity
An ADPLL (all digital phase-locked loop) and a conventional charge-pump PLL (CPPLL) are compared. In the CPPLL, the PFD outputs timed pulses whose duty cycles are proportional to the difference between FREF (reference frequency) and the divided VCO output. Although the pulses have digital waveforms, they don’t represent any digital quantity and need to be converted to an analog VCO control voltage by a charge pump and a loop filter. A charge pump consists of switched current sources to deposit or remove charges in the loop filter. Active amplifiers may be included to enhance performance. These analog circuits suffer from finite transistor output resistance, device mismatch, thermal noise and gate leakage current in highly scaled CMOS processes resulting in compromises in PLL in-band phase noise, loop response, phase locking accuracy, size and power consumption.
To eradicate the aforementioned deficiency, an ADPLL comprising only logic gates except for the digitally controlled oscillator (DCO) to interface with RF world has emerged. The TDC which is analogous to an ADC converts phase errors (PE) into digital quantities. The PE comprehends key information internal to the PLL operations. It can assist built-in self calibration and can be further processed by a DSP to self-assess performance metrics such as phase modulation accuracy in real time without any expensive RF instrument.
The digital loop filter sends bit streams to the DCO. Compared to a VCO, one unique feature is the switched varactors. A DCO does not require continuous frequency tuning but discrete frequency steps. Using low-cost I/O NMOS transistors which share the same implants as those for core NMOS, and taking body effect into account, the Vt is near half Vdd, which is ideal for the switched varactors. The capacitance step c between 0 and 1.4V gate bias is relatively constant. Therefore, the DCO frequency step has a negligible sensitivity to PVT.
Inductors and capacitors occupy most of the space in a DCO. Even though metal-on-metal and gate capacitors shrink less than 30 percent per process node, the inductors take more than half of a DCO real estate. However, as noise and transistor reliability degrade over process scaling, and there has been no major inductor Q enhancement after 65nm, DCO size and voltage swing remain about constant in new processes.
Both analog and digital transmitters convert the signals to digital. The DAC transforms digital quantities to an analog signal which is filtered to remove the sampling images. The reconstructed signal is then upconverted onto an RF carrier and transmitted by a PPA typically at <6 dBm. As new wireless standards demand wider signal bandwidth and higher linearity, it becomes very challenging to maintain amplifier gain, voltage headroom and filter characteristic in new process nodes.
For PPA linearity, a larger backoff from its saturated output power is required to satisfy the increasing peak-to-average power ratio. It is possible to push the PPA operation toward the higher efficiency, then recover the system linearity by digital predistortion (DPD). Since the input signal is completely in digital format, digital signal processing can be deployed for the whole transmitter to form a DTX. The supply voltage can be adaptively reduced according to the instantaneous output power as linearity of individual transistors is no longer important. The overall power consumption can be further improved by using an efficient supply regulator such as a DCDC converter.
Fortunately, the switching operation greatly reduces the DPA sensitivity to transistor Vt and geometrical mismatch, because in each RF period, DPA cells are duty-cycled and stay in deep triode and off states for most of the time. An auxiliary DAC can be used to further compensate random mismatch. In general, intrinsic device matching needs to be >10 bits even for small device sizes. Then, digital techniques are needed to reach a higher resolution.
Digitally-intensive architectures serve as great means to break the tradeoffs between device and circuit limitations. Using algorithms and switching circuits, ADPLL, DRX and DTX have wide spread. High-volume production of SoCs from multiple fabs without any circuit alteration proved that digital architectures can effectively reduce circuit sensitivity to most analog impairments and PVT variations. However, device characteristic such as reliability, noise and mismatch as well as BEOL variability still have major impacts to RF performance. Both device performance and circuit techniques have to be jointly optimized in future process generations.